VOICE THE WAY PTE.LTD.- Advanced Technology

ASIC chips based on Transformer architecture:

Key Technologies and Features of the Transformer Architecture

Fundamental Principles: Words are embedded into vectors, with positional encoding added to capture sequence order—forming matrix X. Multi-head attention then analyzes different parts of the sentence in parallel. This output flows through residual connections, normalization, and a feed-forward network—repeating N times. A final linear layer and Softmax produce the output distribution used for text generation.

KV Cache Core

The KV cache stores user and contextual information, represented as a latent space tensor with shape [B, 1, H]. The data transferred from external memory to on-chip memory has a total size of KV_dim × N_KV_heads × i_token. Based on an estimated processing rate of 1000 tokens per second, the final number of Transformer cores is determined by evaluating bandwidth utilization and the weight residency capacity per core.

Comparison Between Transformer Architecture Inference Chips and General-Purpose GPUs Core Metrics Comparison:

● Flexible hardware architecture that supports products ranging from small models (1B parameters) to large models (10,000B parameters), and is backward compatible with ultra-large conversational/video models (400B, 1000B, 10,000B, etc.).

● Built on a proprietary architecture, our solution simplifies three core challenges—bandwidth, capacity, and interconnect—into one decisive target: KV cache read bandwidth. With ASIC-level acceleration, we deliver customizable, high-performance chips that flexibly balance cost, memory configuration, and advanced process choices—purpose-built for next-generation AI workloads.

Advanced Technology

Products and Applications:

Edge Computing

Network Switching Chip

● Parallel Network Intelligence

VTW’s chip features a multi-core architecture capable of parallel processing for traffic policy execution, security enforcement, and system log management. It ensures stable performance under varying network loads, while dynamically adjusting power based on real-time demand.

● High-Performance Switching Matrix

The chip includes a non-blocking switching matrix at the heart of data forwarding. It supports multi-port parallel transmission and uses optimized routing algorithms to achieve high throughput and low latency, preventing congestion and ensuring seamless data flow.

● High-Speed Interface Modules

VTW’s chip integrates high-speed I/O interfaces, including 10G/25G/100G SerDes and PCIe 5.0/6.0. These enable fast interconnection with external devices and support rapid data storage or functional expansion, while maintaining compatibility with diverse network protocols.

● Reliable MAC Layer Operations

Multiple MAC (Media Access Control) modules work in coordination to manage Ethernet and other link-layer protocols, handling frame encapsulation, decapsulation, and error correction. This ensures reliable link-layer transmission and effective control of physical interfaces.

● Integrated High-Speed Memory

The chip incorporates large-capacity DDR4/DDR5 memory to store network data, protocol stacks, routing tables, and system software. Its memory controller is tightly integrated with the ARM SoC and switching matrix to optimize caching, read/write speed, and overall performance.

● Precision Timing, Power & Security

- Clock module provides precise synchronization for all components

- Power management module dynamically regulates power to optimize energy use

- Configuration module allows flexible initialization and tuning

- Security module enables encryption and authentication to ensure data integrity

Video Processing Chip