Introduction:
VTW delivers end-to-end ASIC design services that transform your ideas into silicon—fast. From architecture definition and IP selection to RTL, DFT, physical design, verification, and volume production, we manage the entire flow with precision and flexibility. We don’t just build chips—we help you build competitive advantages.
Our platform-based and customized design model enables clients to:
● Launch differentiated products
● Shorten time-to-market
● Maximize performance per watt
Our expertise spans across edge computing, high-performance computing (HPC), and communication switching, where speed, efficiency, and scalability matter most.With access to a broad network of top-tier IP partners, we integrate advanced IP blocks tailored to your use case—accelerating deployment and de-risking development from day one.
Strategic IP Ecosystem Partnerships VTW collaborates with world-class IP providers, including:
●Synopsys – Specializing in SerDes transceivers and high-speed communication IPs
●AlphaWave – Providing 112G PAM4 PHY and low-power interconnect solutions
●Cadence – Supporting a complete SoC design flow with high-speed PHY IPs and design platforms
Together we are co-developing a custom switching ASIC designed for data center and AI infrastructure, featuring high throughput, low latency, and high integration.
VTW Key Responsibilities:
●Leading ASIC SoC architecture and packet pipeline design
●Managing the Chip design and coordinating with leading foundries (TSMC / Samsung) on advanced process nodes (N5/N4P)
●Coordinating with OEMs to deliver modular switch platforms optimized for SONiC/SAI stack
Core Mission:
●To develop a customized, high-performance switching chip platform tailored for data center environments.
Project Positioning:
●Deep collaboration with leading ecosystem partners, including Cadence, Synopsys, AlphaWave, and TSMC.
Market Opportunity:
●The global Data Center Interconnect (DCI) switching chip market is valued in the 10B range
●AI and large language models are driving surging demand for east-west traffic switching chips
Product & Technology:
●ASIC Architecture: 25.6 Tbps single-die design (Non-Chiplet) using TSMC/Samsung 5nm or 4P process
●Supports 112G PAM4 SerDes (via AlphaWave IP) and 12G control channels Integrated programmable packet processing engine with support for P4
language and SONiC drivers
●Multi-tenant / sliceable architecture, supporting AI clusters, data centers, and edge computing scenarios
Customers and Partners
IP Services
Based on customer requirements, we leverage abundant third-party IP resources, technical support, and project experience to provide IP services applicable across multiple fields, primarily including DDR, PCIe, HDMI, MIPI, and USB. These technologies feature verified reliability, reusability, and specific functionalities that help improve design efficiency. They can be used in independent design phases or directly licensed to clients for design and development. Currently, these IP services are widely applied in the design of various IC products across fields such as edge computing, communication switching (switch), and high-performance computing (HPC).
Customized ASIC Design
Advantages:
Expertise and Innovation: Leveraging deep industry experience and innovative approaches to deliver industry-leading solutions.
Scalability: The service can adapt to projects of various sizes, ensuring the design can flexibly scale.
Customized Services: Tailoring solutions based on clients’ specific requirements to ensure the design meets the desired objectives.
Faster Time-to-Market: Efficient design practices shorten product launch cycles, enhancing market competitiveness.
Switch Chip Architecture
Throughput: 25.6 Tbps
The interconnect architecture is centered around a Switch Fabric, which connects various Master and Slave modules via an AXI bus. The VOQ (Virtual Output Queue) buffer is managed through an AXI Lite control interface, enabling flow queue status monitoring and control.
